Trying to make sense of the Pac-Man hardware

I've started to try to learn VHDL programming so that I can help out implementing old arcade hardware on FPGA chips, like those from Xilinx. Mike J's FPGA Arcade has excellent example implementations. The one that I'm trying to learn from is Pac-Man.

I downloaded the schematics for Pac-Man from http://tamdb.net/ and I'm starting to compare the schematics to Mike J's implementation here.

This part of the schematic shows a ROM that is used as a pallette lookup that takes in 4-bit values and spits out 8-bit colors that are RGB-332 (3 bits for red and green 2 bits for blue)



This is the VHDL code generated by MikeJ's romgen for the rom file "82s123.7f" which lives in the pacrom_7f_dst.vhd file (note: I changed all the ROM contents to "00" to avoid violating copyright.)

-- generated with romgen v3.0 by MikeJ
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.numeric_std.all;

library UNISIM;
  use UNISIM.Vcomponents.all;

entity PACROM_7F_DST is
  port (
    ADDR        : in    std_logic_vector(3 downto 0);
    DATA        : out   std_logic_vector(7 downto 0)
    );
end;

architecture RTL of PACROM_7F_DST is

  signal rom_addr : std_logic_vector(11 downto 0);

begin

  p_addr : process(ADDR)
  begin
     rom_addr <= (others => '0');
     rom_addr(3 downto 0) <= ADDR;
  end process;

  p_rom : process(rom_addr)
  begin
    DATA <= (others => '0');
    case rom_addr is
      when x"000" => DATA <= x"00";
      when x"001" => DATA <= x"00";
      when x"002" => DATA <= x"00";
      when x"003" => DATA <= x"00";
      when x"004" => DATA <= x"00";
      when x"005" => DATA <= x"00";
      when x"006" => DATA <= x"00";
      when x"007" => DATA <= x"00";
      when x"008" => DATA <= x"00";
      when x"009" => DATA <= x"00";
      when x"00A" => DATA <= x"00";
      when x"00B" => DATA <= x"00";
      when x"00C" => DATA <= x"00";
      when x"00D" => DATA <= x"00";
      when x"00E" => DATA <= x"00";
      when x"00F" => DATA <= x"00";
      when others => DATA <= (others => '0');
    end case;
  end process;
end RTL;

Note the resistors on the color outputs. These are used to convert from digital to analog. The higher the resistance, the less significant the bit is.