GaryMcT's blog

Books about digital electronics and FPGA development that I like

2010-02-09T08:00:00.000-08:00

You end up coding in VHDL (or Verilog) for this stuff. This book is great for learning the language:

http://www.amazon.com/gp/aw/d.html/ref=redir_mdp_mobile/187-0765075-2752924?redirect=true&ref_=oss%5Fproduct&a=0262162245

This one is great if you are an electronics newb (like me) and want to learn enough to do FPGA programming:

http://www.amazon.com/gp/aw/d.html/ref=redir_mdp_mobile/187-0765075-2752924?redirect=true&ref_=oss%5Fproduct&a=0131733494

This last one is pretty expensive, but avoid the paperback version that is for sale on Amazon. It's a really poor printing (can't read a lot of the pages) that is made only for India and isn't supposed to be sold in the US.

Pac-Man Logic Board Schematic Revision B

2010-02-07T00:39:00.000-08:00

I scanned in the 3 pages and did the photoshop work for the pac-man logic board version b schematic. This is nice for panning around the whole schematic on your computer with no page breaks. This looks higher quality than most of the scans that I've seen out there, so I figured I'd share:

Pac-Man Logic Board Schematic Revision B

Another site/forum on FPGA implementations of video games

2010-01-23T21:22:00.000-08:00

PaceDev Forum

Good page on Pac-Man color/sprite ROMs

2010-01-23T00:17:00.001-08:00

http://www.lomont.org/Software/Games/PacMan/PacmanEmulation.htm

color ROM 4a on the Pac-Man board

2010-01-22T20:38:00.000-08:00

Every sprite (and I believe the background) in Pac-Man has at most 4 colors in it. Of the 4 colors, there is a 4-bit index into the palette ROM 7f mentioned in the previous post. Palette index 0 is transparent for sprites (and I assume black for the background?)

Here's the VHDL code for the ROM as generated by Mike J's romgen. Note that I've modified each x"00" through x"0f" value (4-bit palette index) to zero to avoid publishing the ROM data:



-- generated with romgen v3.0 by MikeJ
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.numeric_std.all;

library UNISIM;
  use UNISIM.Vcomponents.all;

entity PACROM_4A_DST is
  port (
    ADDR        : in    std_logic_vector(7 downto 0);
    DATA        : out   std_logic_vector(7 downto 0)
    );
end;

architecture RTL of PACROM_4A_DST is

  signal rom_addr : std_logic_vector(11 downto 0);

begin

  p_addr : process(ADDR)
  begin
     rom_addr <= (others => '0');
     rom_addr(7 downto 0) <= ADDR;
  end process;

  p_rom : process(rom_addr)
  begin
    DATA <= (others => '0');
    case rom_addr is
      when x"000" => DATA <= x"00";
      when x"001" => DATA <= x"00";
      when x"002" => DATA <= x"00";
      when x"003" => DATA <= x"00";
      when x"004" => DATA <= x"00";
      when x"005" => DATA <= x"00";
      when x"006" => DATA <= x"00";
      when x"007" => DATA <= x"00";
      when x"008" => DATA <= x"00";
      when x"009" => DATA <= x"00";
      when x"00A" => DATA <= x"00";
      when x"00B" => DATA <= x"00";
      when x"00C" => DATA <= x"00";

SNIP

      when x"0FC" => DATA <= x"00";
      when x"0FD" => DATA <= x"00";
      when x"0FE" => DATA <= x"00";
      when x"0FF" => DATA <= x"00";
      when others => DATA <= (others => '0');
    end case;
  end process;
end RTL;

Trying to make sense of the Pac-Man hardware

2010-01-22T01:07:00.001-08:00

I've started to try to learn VHDL programming so that I can help out implementing old arcade hardware on FPGA chips, like those from Xilinx. Mike J's FPGA Arcade has excellent example implementations. The one that I'm trying to learn from is Pac-Man.

I downloaded the schematics for Pac-Man from http://tamdb.net/ and I'm starting to compare the schematics to Mike J's implementation here.

This part of the schematic shows a ROM that is used as a pallette lookup that takes in 4-bit values and spits out 8-bit colors that are RGB-332 (3 bits for red and green 2 bits for blue)

This is the VHDL code generated by MikeJ's romgen for the rom file "82s123.7f" which lives in the pacrom_7f_dst.vhd file (note: I changed all the ROM contents to "00" to avoid violating copyright.)


-- generated with romgen v3.0 by MikeJ
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.numeric_std.all;

library UNISIM;
  use UNISIM.Vcomponents.all;

entity PACROM_7F_DST is
  port (
    ADDR        : in    std_logic_vector(3 downto 0);
    DATA        : out   std_logic_vector(7 downto 0)
    );
end;

architecture RTL of PACROM_7F_DST is

  signal rom_addr : std_logic_vector(11 downto 0);

begin

  p_addr : process(ADDR)
  begin
     rom_addr <= (others => '0');
     rom_addr(3 downto 0) <= ADDR;
  end process;

  p_rom : process(rom_addr)
  begin
    DATA <= (others => '0');
    case rom_addr is
      when x"000" => DATA <= x"00";
      when x"001" => DATA <= x"00";
      when x"002" => DATA <= x"00";
      when x"003" => DATA <= x"00";
      when x"004" => DATA <= x"00";
      when x"005" => DATA <= x"00";
      when x"006" => DATA <= x"00";
      when x"007" => DATA <= x"00";
      when x"008" => DATA <= x"00";
      when x"009" => DATA <= x"00";
      when x"00A" => DATA <= x"00";
      when x"00B" => DATA <= x"00";
      when x"00C" => DATA <= x"00";
      when x"00D" => DATA <= x"00";
      when x"00E" => DATA <= x"00";
      when x"00F" => DATA <= x"00";
      when others => DATA <= (others => '0');
    end case;
  end process;
end RTL;

Note the resistors on the color outputs. These are used to convert from digital to analog. The higher the resistance, the less significant the bit is.